18nm n-channel and p-channel Dopingless Asymmetrical Junctionless DG-MOSFET: Low Power CMOS Based Digital and Memory Applications

In this paper, an 18nm dopingless asymmetrical junctionless (AJ) double gate (DG) MOSFET has been designed for suppressed short channel effects (SCEs) low power applications. A desired ON and OFF state current ratio with subthreshold performance parameters under limit, is the major focus of proposed transistor. Different sensitivity AJ DG such as drain extension, length overlapping oxide thickness are compared doped region. The ON-state obtained 3.80 x $${10}^{-6 }$$ A/µm reduced OFF-state leakage up to1.37 $${10}^{-17 A/µm. slope (SS) induced barrier lowering (DIBL) device 59.5 mV/decade 10.5 mV/V respectively. Temperature analysis at various temperature 250 K,300 K, 350 400 K shows a small variation in (< 15 %). Additionally, p-channel along n-channel their evaluated CMOS inverter circuit 6T SRAM cell. All design have done 2D/3D Visual TCAD simulator.